1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor device with a fuse circuit, and a method for driving the same.
2. Description of the Related Art
In general, a semiconductor device includes a fuse circuit for storing various pieces of information for setting an operation environment. For example, redundancy information corresponding to defects, trimming information for internal voltages, mode register set (MRS) information, and so on are stored in the fuse circuit.
Fuse circuits may be classified into physical fuse circuits, where the connection is controlled by laser radiation, and electrical fuse circuits, where the connection is controlled by an electrical signal.
Recently electrical fuse circuits have been widely used because, as opposed to physical fuse circuits, the connection of the electrical fuse circuit is controllable at a package level.
FIG. 1 is a block diagram illustrating a conventional semiconductor device 100.
Referring to FIG. 1, the conventional semiconductor device 100 includes a first fuse circuit 110, an internal voltage generation circuit 120, and a second fuse circuit 130. The first fuse circuit 110 outputs internal voltage setting signals SRE_FUSE<0:n> for trimming an internal voltage by using an external voltage VEXT in a power-up mode. The internal voltage generation circuit 120 generates the internal voltage VIN in response to the internal voltage setting signals SRE_FUSE<0:n>. The second fuse circuit 130 outputs repair signals ARE_FUSE<0:m> by using the internal voltage VIN in a boot-up mode.
The power-up mode is a power-up section where the external voltage VEXT is supplied during an initial operation of the conventional semiconductor device 100, and the external voltage VEXT rises from a ground voltage VSS level to a predetermined target level in the power-up section. A power-up signal PWRUP rises corresponding to the external voltage VEXT in the power-up section and then maintains the ground voltage VSS level when the external voltage VEXT rises over the predetermined target level.
The boot-up mode is a section where a plurality of fuse signals, programmed in the second fuse circuit 130, is sequentially read out, and a boot-up operation is normally performed when the internal voltage VIN is set up. The boot-up mode may be entered by a reset signal RESETB inputted from an exterior. Although it is not illustrated in the drawing, the boot-up mode may be entered by an internal signal enabled a predetermined time after the power-up mode is completed.
FIG. 2 is a detailed block diagram of the first fuse circuit 110 shown in FIG. 1.
Referring to FIG. 2, the first fuse circuit 110 includes a plurality of single e-fuse circuits SRE0 to SREn and a first sense amplification unit SRE_S/A. The single e-fuse circuits SRE0 to SREn are programmed by a rupture command Rupture_CMD and generate respective first fuse signals SRE<0> to SRE<n> corresponding to whether the single e-fuse circuits SRE0 to SREn are programmed or not. The first sense amplification unit SRE_S/A generates the internal voltage setting signals SRE_FUSE<0:n> in response to the power-up signal PWRUP and the first fuse signals SRE<0> to SRE<n>.
Each of the single e-fuse circuits SRE0 to SREn include an input unit INT for receiving the rupture command Rupture_CMD, a driving unit P for supplying the external voltage VEXT to a sense amplification node ND in response to the rupture command inputted through the input unit INT, and an e-fuse, which is coupled between the sense amplification node ND and a low voltage terminal VBBF.
Although it is not illustrated in the drawing, the first sense amplification unit SRE_S/A includes a plurality of latch units for latching the fuse signals SRE<0> to SRE<n> in response to the power-up signal PWRUP.
FIG. 3 is a detailed block diagram of the second fuse circuit 130 shown in FIG. 1. FIGS. 4A and 4B are detailed diagrams for describing an operation of a fuse cell included in a fuse array shown in FIG. 3.
Referring to FIG. 3, the second fuse circuit 130 includes a fuse array 131, a row driving unit 133, a redundancy fuse array 135, a redundancy row driving unit 137, and a second sense amplification unit 139. The fuse array 131 is coupled with a plurality of row select lines WL<0> to WL<120> and a plurality of column select lines BL<0> to BL<39>. The row driving unit 133 activates one among the row selection lines WL<0> to WL<120>. The redundancy fuse array 135 is coupled with a plurality of redundancy row selection lines RWL<0> to RWL<120> and the column selection lines BL<0> to BL<39>. The redundancy row driving unit 137 activates one among the redundancy row selection lines RWL<0> to RWL<120>. The second sense amplification unit 139 generates the repair signals ARE_FUSE<0:m> by sensing and amplifying a plurality of second fuse signals of the column selection lines BL<0> to BL<39>.
The fuse array 131 includes fuse cells, which are formed at every intersection of the row selection lines WL<0> to WL<120> and the column selection lines BL<0> to BL<39>. As shown in FIG. 4A, each of the fuse cells include a fuse F coupled with a row fuse line WLPG<#> and a switching unit N for selectively coupling the fuse F with a column selection line BL<#> based on whether a row selection line WL<#> is activated or not. As a program voltage VPG is supplied to the row fuse line WLPG<#>, and a selection voltage VWL is supplied to the row selection line WL<#>, and a ground voltage VSS is supplied to the column selection line BL<#> in a program mode, a high voltage difference between both terminals of the fuse F occurs and the fuse F is changed from a high resistance state to a low resistance state. For example, the program voltage VPG is 5V and the selection voltage VWL is 2V in the program mode. FIG. 4B shows that the fuse F is programmed and changed to the low resistance state. When the fuse F is programmed, as a read voltage VPG is supplied to the row fuse line WLPG<#> and the selection voltage VWL is supplied to the row selection line WL<#> in a boot-up mode, a current Isa corresponding to the read voltage VPG flows through the column selection line BL<#>. For example, the read voltage VPG is 2V and the selection voltage VWL is 1V in the boot-up mode.
FIG. 3 illustrates the row selection lines WL<0> to WL<120> between the row driving unit 133 and the fuse array 131, and FIG. 4 illustrates a plurality of row fuse lines WLPG<0> to WLPG<120> between the row driving unit 133 and the fuse array 131.
The redundancy fuse array 135 and the redundancy row driving unit 137 shown in FIG. 3 are formed to improve operation reliability of the fuse array 131 and the row driving unit 133 and perform the same operation as the fuse array 131 and the row driving unit 133 and thus detailed descriptions are omitted.
Operation of a conventional semiconductor device 100 having the above-described structure is described next.
A fuse program operation is performed to the first fuse circuit 110 and the second fuse circuit 130 based on system requirements set in a test mode. For example, an e-fuse E-FUSE included in a corresponding single e-fuse circuit SRE# is programmed in the first fuse circuit 110 based on a rupture command Rupture_CMD, and as a corresponding row selection line WL<#> and a corresponding column selection line BL<#> are selected and a program voltage VPG is supplied through a corresponding row fuse line WLPG<#>, a corresponding fuse F is programmed in the second fuse circuit 130.
When entered in a power-up mode, the first fuse circuit 110 reads out a plurality of first fuse signals SRE<0> to SRE<n> programmed in a plurality of single e-fuse circuits SRE0 to SREn and generates internal voltage setting signals SRE_FUSE<0> to SRE_FUSE<n> corresponding to the read-out first fuse signals SRE<0> to SRE<n>. The first fuse signals SRE<0> to SRE<n> are read out simultaneously and are latched as the internal voltage setting signals SRE_FUSE<0> to SRE_FUSE<n>.
The internal voltage generation circuit 120 generates a predetermined internal voltage VIN in response to the internal voltage setting signals SRE_FUSE<0> to SRE_FUSE<n>.
Subsequently, when entered in a boot-up mode, the second fuse circuit 130 reads out a plurality of second fuse signals programmed in the fuse array 131 and then generates the repair signals ARE_FUSE<0> to ARE_FUSE<m> corresponding to the read-out second fuse signals. The second fuse signals are sequentially read out by the row driving unit 133 and the second sense amplification unit 139 and are sequentially latched as the repair signals ARE_FUSE<0> to ARE_FUSE<m>.
In conclusion, the conventional semiconductor device 100 controls an internal voltage generation operation which must be performed prior to the boot-up mode. The conventional semiconductor device 100 controls the internal voltage generation operation through the first fuse circuit 110 in the power-up mode and normally reads out fuse signals programmed in the second fuse circuit 130 as entering the boot-up mode when the internal voltage is in a stable state.
Since a conventional semiconductor device 100 having the above-described structure reads out the first fuse signals SRE<0> to SRE<n> corresponding to the internal voltage setting signals SRE_FUSE<0> to SRE_FUSE<n> at once in the power-up mode, the conventional semiconductor device 100 does not need time to boot up and has an advantage in reading out plenty of second fuse signals in the boot-up mode.
However, the conventional semiconductor device 100 has concerns in that it may not be controlled and its processes are complicated since the first fuse circuit 110 and the second fuse circuit 130 are formed differently from one another.